1. Field of the Invention
The present invention relates to an ATM(Asynchrnous Transfer Mode) switch interface apparatus for frame relay interworking, and in particular, to an improved ATM switch interface apparatus for frame relay interworking which is capable of receiving a user cell from a FRIA (Frame Relay Interface Apparatus), performing a connection identifier-based usage parameter control function, transmitting the IPC cell received from the FRIA through a IPC bus and a user cell in which a traffic is valid to an ATM switch by synchronizing a module clock received from a clock generator, analyzing the head data of the ATM cell received from the ATM switch when the data corresponds to a user cell, transmitting the cell to a corresponding FRIA based on a corresponding virtual path identifier and a virtual channel identifier value and allowing a processor to process the cell using an AAL5 reassembly in the case of an IPC (Inter Processor Communication) cell and an OAM (Operation and Maintenance) cell.
2. Description of the Prior Art
At an initial stage of the ATM service, a high speed data communication service such as a frame relay, a SMDS (Switched Multi-megabit Data Service), a circuit emulation, etc. will be available. The frame relay, SMDS, and leased line service may be provided using an independent network which is built by the type of each service. In view of the operator of the network, the ATM backbone network is implemented for the purpose that all existing services and future services may be available as one integrated service network. Therefore, for the ATM switching system, the frame relay interworking apparatus is developed for the existing services such as the service implemented based on the ATM, the existing frame relay service, etc.
In addition, the B-ISDN (Broadband-Integrated Service Digital Network) has an advantages in that it is possible to provide various services using an effective network resource. Therefore, in the industry, an ATM network and an ATM switch have been developed for implementing a high speed broadband communication such as a high speed data transmission, a video communication, etc. However, since the ATM network is able to provide a frame relay service, there is a disadvantage in that an ATM switch interface function is needed, in which the data of the frame unit is converted into an ATM cell and interfaced with the ATM switch.
Accordingly, it is an object of the present invention to provide an ATM switch interface apparatus for frame relay interworking which overcomes the aforementioned problems encountered in the conventional art.
It is another object of the present invention to provide an ATM switch interface apparatus for frame relay interworking which is capable of receiving a user cell from a FRIA (Frame Relay Interface Apparatus), performing a connection identifier-based usage parameter control function, transmitting a user cell in which a traffic is valid and the IPC cell received from the FRIA through a IPC bus to an ATM switch by synchronizing a module clock received from a clock generator, analyzing the head data of the ATM cell received from the ATM switch when the data corresponds to a user cell, transmitting the cell to a corresponding FRIA based on a corresponding virtual path identifier and a virtual channel identifier value and allowing a processor to process the cell using an AAL5 reassembly in the case of an IPC (Inter Processor Communication) cell and an OAM (Operation and Maintenance) cell.
In order to achieve the above objects, there is provided an ATM switch interface apparatus for frame relay interworking which includes an up stream cell flow interface which consists of an up stream cell transmission request signal, a FIFO read enable signal, a read clock signal, and a 16 bit data bus; a buffer for decreasing an effect of an external noise with respect to a cell inputted through the up stream cell flow interface; a cell bus receiving controller (CBRC) including a data register for storing the cell inputted through the buffer and a control register in order for a processor to perform a registration, deletion and enquiry of a connection, performing a up stream cell transmission request signal checking operation, a FIFO read enable signal generating function, a content address memory (CAM) and a usage parameter control FIFO (UPC FIFO); a UPC for checking a user cell traffic with respect to the cell stored in the UPC FIFO and UPC memories for storing a control data and a statistic data; a user cell for storing a user cell passed through the UPC; an IPC cell transmitting FIFO for storing an IPC cell and an OAM cell that the processor transmits to the ATM switch; a control signal generator for controlling an ALL5 cell segmentation for storing the IPC cell and OAM cell into the ITFIFO and generating a chip selection signal of a 4 Mbyte data memory; a buffer for receiving an FRIA state management message inputted via the IPC bus and controlling a data bus; a processor for processing a state management message inputted from the buffer and storing the cell transmitted to the ATM switch into the SPM memory and controlling the entire operation; an AAL5 cell segmentation, packet memories of a 128 Kbyte, and control memories of 128 Kbyte; a cell multiplexer for reading the cell stored in the FIFO when more than one cell from the UFIFO and ITFIFO is stored, performing a head conversion using a connection identifier of the cell head, generating an HEC with respect to a head 7 byte, creating an odd parity bit and transmitting the cell to the link interface unit in synchronization with a 23.4747 MHz clock signal; a cell head conversion table (HCT) including a 32 Kbyte DPRAM for storing a head conversion table transmitted from the processor so that the cell multiplexer performs a head conversion; a switch link transmitting and receiving unit for converting an odd parity generation and checking data, a head error control (HEC) generation and checking data and a parallel data with respect to the cell inputted from the cell multiplexer (MUX) into a serial data, transmitting the thusly converted data to the LLIA of the ATM switch through a ground-shielded cable, converting the serial data received from the LLIA into a parallel data, generating an odd parity bit and transmitting to the cell demultiplexer; a cell demultiplexer for receiving the cell from the LTRI, identifying a user cell and an IPC cell, transmitting the user cell to the FRIA or the IPC cell and the OAM cell to the IRFIFO; an AAL5 reassembling unit for reassembling the cell stored in the IRFIFO in the form of the AAL5, 128 Kbyte packet memories, and 128 Kbyte control memories; a buffer for controlling a 16 bit data bus transmitted from the cell demultiplexer; and a clock receiver for receiving a clock of an ECL level from the FCDA interface and providing the thusly received clock to the LTRI, CBRC and MUX, respectively.
Additional advantages, objects and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.